1. Field of the Invention
The present invention relates to a differential amplifier circuit and more particularly, to a differential amplifier circuit to be formed on Complementary Metal Oxide Semiconductor (CMOS) integrated circuits or on bipolar integrated circuits, which has an improved transconductance linearity.
2. Description of the Prior Art
FIG. 1 shows an example of conventional differential amplifier circuits with a CMOS structure whose transconductance linearity is improved.
The differential amplifier circuit shown in FIG. 1 is composed of a first differential pair of MOS transistors M11 and M12 which are driven by a constant current source 51 (current: I.sub.0) and a second differential pair of MOS transistors M13 and M14 which are driven by a constant current source 52 (current: aI.sub.0, a.noteq.1). The transistor M11 has the same ratio (W/L) between its gate length L and gate width W as that of the transistor M12, and the transistor M13 has the same ratio (W/L) between its gate length L and gate width W as that of the transistor M14. When the transconductance parameters of the transistors M11 and M12 are both defined as .beta., the transconductance parameters of the transistors M13 and M14 are b.beta. where b.noteq.1, respectively.
The transconductance parameter .beta. is expressed as EQU .beta.=.mu.(C.sub.OX /2)(W/L) (1)
where .mu. is the effective surface carrier mobility and C.sub.OX is a gate-oxide capacity per unit area.
In FIG. 1, the gates of the transistors M11 and M14 coupled together and the gates of the transistors M12 and M13 coupled together form differential input ends of the differential amplifier circuit. An input voltage V.sub.in is applied to the differential input ends.
The drains of the transistors M11 and M13 coupled together and the drains of the transistors M12 and M14 coupled together form differential output ends of the differential amplifier circuit.
The sources of the transistors M11 and M12 are connected in common to the constant current source 51 and the sources of the transistors M13 and M14 are connected in common to the constant current source 52.
Assuming that the transistors M11, M12, M13 and M14 are operating at their saturation regions, drain currents I.sub.d11 and I.sub.d12 of the transistors M11 and M12 are respectively expressed as the following equations (2-1) and (2-2) using the transconductance parameter .beta., the threshold voltage V.sub.TH of the transistors M11, M12, M13 and M14 and gate-source voltages V.sub.GS11 and V.sub.GS12 of the transistor M11 and M12. EQU I.sub.d11 =.beta.(V.sub.GS11 -V.sub.TH).sup.2 ( 2-1) EQU I.sub.d12 =.beta.(V.sub.GS12 -V.sub.TH).sup.2 ( 2-2)
The drain currents I.sub.d11 and I.sub.d12 satisfies the relationship as I.sub.d11 +I.sub.d12 =I.sub.0.
Accordingly, the difference of the drain currents I.sub.d11 and I.sub.d12 is given as the following equations (3-1), (3-2) and (3-3). ##EQU1##
In the equations (3-1), (3-2) and (3-3), the input voltage V.sub.in satisfies the expression as V.sub.in =V.sub.GS11 -V.sub.GS12.
Drain currents I.sub.d13 and I.sub.d14 of the transistors M13 and M14 can be expressed as equations similar to the equations (2-1) and (2-2), respectively. Here, the drain currents I.sub.d13 and I.sub.d14 satisfies the relationship as I.sub.d13 +I.sub.d14 =aI.sub.0, so that the difference of the drain currents I.sub.d13 and I.sub.d14 is expressed as the following equations (4-1), (4-2) and (4-3), where a&lt;(a/b)&lt;1. ##EQU2##
The differential output current .increment.I of the differential amplifier circuit shown in FIG. 1 is given as the following equations (5-1), (5-2) and (5-3). ##EQU3##
The differential output current .increment.I shown as the equations (5-1), (5-2) and (5-3) is differentiated by the input voltage V.sub.in. To make the transconductance substantially constant in the equations (5-1), (5-2) and (5-3), the values of the equation obtained by the differentiation when V.sub.in =0 and .vertline.V.sub.in .vertline.={(aI.sub.0)/(b.beta.)}.sup.1/2 are required to be equal to each other. Therefore, the following relationship has to be satisfied as EQU 1=(b.multidot.b.sup.1/2)/a.sup.1/2 ( 6)
FIG. 2 shows the transconductance characteristics of the conventional differential amplifier circuit shown in FIG. 1 with the constants a and b as parameters. In FIG. 2, it is seen that the fluctuation of the transconductance is limited to 3% or less in the input voltage range of .vertline.V.sub.in .vertline..ltoreq.0.7(I.sub.0 /.beta.).sup.1/2.
FIG. 3 shows another example of the conventional differential amplifier circuits whose transconductance is good in linearity, which is disclosed by A. Nedungadi and T. R. Viswanathan in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, Vol. CAS-31, No.10, pp. 891-894, October 1984, entitled "Design of Linear CMOS transconductance Elements".
In this paper, they supposed that when the gate lengths of two MOS transistors forming each unbalanced differential pair were equal to each other, the differential amplifier circuit which are composed of two of the unbalanced differential pairs whose output ends are cross-coupled would have improved linearity of the transconductance if a ratio of the gate widths of the MOS transistors forming each unbalanced differential pair were larger. Then, they obtained a conclusion through the SPICE simulation in which the ratio of the gate widths are 10 and 20 and that the ratio of the gate widths was required to be 10 or more.
Additionally, they thought that the above-mentioned conclusion is not practical since such a large ratio as 10 or more leads to a large chip area. Therefore, they proposed the differential amplifier circuit shown in FIG. 3.
In FIG. 3, there is provided a "Cross-Coupled Quad Cell" formed of MOS transistors M21, M22, M23 and M24 as a squaring circuit thereby to improve the transconductance linearity of a balanced differential pair formed of MOS transistors M26 and M27 having the same gate-width to gate-length ratio (W/L).
The MOS transistors M21 and M24 compose a first differential pair and the MOS transistors M23 and M22 compose a second differential pair. The first differential pair is driven by a constant current source 61 which is connected to the common-connected sources of the transistors M21 and M24 and generates a constant current (n+1)I. The second differential pair is driven by a constant current source 62 which is connected to the common-connected sources of the transistors M23 and M22 and generates a constant current (n+1)I.
The transconductance parameters of the transistors M21 and M22 are k.sub.0 and those of the transistors M23 and M24 are n times as much as k.sub.0, or nk.sub.0. The MOS transistor with the transconductance parameter nk.sub.0 is generally realized by n in number of the unit transistors with the transconductance parameter k.sub.0 which are connected in parallel.
The MOS transistors M26 and M27 whose sources are connected in common at a point B compose a differential pair, which is driven by a constant current source 63 generating a constant current aI. The constant current source 63 is connected to the differential pair at the point B and generates a constant current aI. The transconductance parameters of the transistors M26 and M27 are k.sub.0.
The gates of the transistors M26, M21 and M23 are coupled together to be applied with a first input voltage V.sub.1. The gates of the transistors M27, M22 and M24 are coupled together to be applied with a second input voltage V.sub.2.
The drains of the transistors M23 and M24 are connected in common to a voltage source (voltage:V.sup.+). The drains of the transistors M21 and M22 are coupled together at a point A, and between the drains thus coupled together and the voltage source, there is provided with a constant current source 64 which generates a constant current aI. An MOS transistor 25 whose drain and gate are connected to each other is provided between the points A and B. The transistor M25 serves as a current level shifter for shifting the current level at the point A to that at the point B.
MOS transistors M28 and M29 compose a current mirror circuit serving as an active load of the differential amplifier circuit. An output current i of the differential amplifier circuit is derived from the drain of the transistor M29.
In the conventional differential amplifier circuit shown in FIG. 3, in the range of .vertline.x.vertline..ltoreq.(n+1).sup.1/2 where V.sub.1 -V.sub.2 =v and x=v/(I/k.sub.0).sup.1/2, the drain current I.sub.D21, I.sub.D22, I.sub.D23 and I.sub.D24 of the transistors M21, M22, M23 and M24 are expressed as the following equations (7-1), (7-2), (7-3) and (7-4), respectively. EQU I.sub.D21 =I[1+.gamma.x.sup.2 +(.alpha./2).times.(1-.beta.x.sup.2).sup.1/2 ](7-1) EQU I.sub.D22 =I[1+.gamma.x.sup.2 +(.alpha./2).times.(1-.beta.x.sup.2).sup.1/2 ](7-1) EQU I.sub.D23 =I[n-.gamma.x.sup.2 +(.alpha./2).times.(1-.beta.x.sup.2).sup.1/2 ](7-3) EQU I.sub.D24 =I[n-.gamma.x.sup.2 +(.alpha./2).times.(1-.beta.x.sup.2).sup.1/2 ](7-4)
In the equations (7-1), (7-2), (7-3) and (7-4), .alpha., .beta. and .gamma. are defined as the following expressions (8-1), (8-2) and (8-3), respectively. EQU .alpha.=4n/(n+1) (8-1) EQU .beta.=n/(n+1).sup.2 ( 8-2) EQU .gamma.=n(n-1)/(n+1).sup.2 ( 8-3)
The drain current I.sub.D21, I.sub.D22, I.sub.D23 and I.sub.D24 and the constant currents (n+1)I of the current sources 61 and 62 satisfy the following relationship as EQU I.sub.D21 +I.sub.24 =I.sub.D22 +I.sub.D23 =(n+1)I (9)
Accordingly, the sum (I.sub.D21 +I.sub.D22) of the drain currents I.sub.D21 and I.sub.D22 can be expressed as the following equation (10) and the drain currents I.sub.D25 of the transistor M25 can be expressed as the following equation (11). EQU I.sub.D21 +I.sub.D22 =2I[1+.gamma.x.sup.2 ]=2I+{2n(n-1)/(n+1).sup.2 }Ix.sup.2 ( 10) EQU I.sub.D25 =aI-(I.sub.D21 +I.sub.D22) (11)
Here, the current of the balanced differential pair of the transistors M26 and M27 is defined as I.sub.0, then the output current is expressed as the following equation (12). EQU i=I.sub.D6 -I.sub.D7 =k'V {2I.sub.0 /k')-v.sup.2 }.sup.1/2 (.vertline.v.vertline..ltoreq.(I.sub.0 k').sup.1/2) (12)
The current I.sub.0 satisfies the relationship as ##EQU4##
Thus, if the equation (13) is substituted into the equation (12), the output current i can be expressed as ##EQU5##
If the relationship between k.sub.0 and k' is selected as the following expression (15), the output current i is obtained as the following equation (16). ##EQU6##
It is seen from the equation (16) that the differential amplifier circuit shown in FIG. 3 has a very good transconductance linearity.
FIG. 4 shows still another example of the conventional differential amplifier circuits to be formed on bipolar integrated circuits, which is disclosed by M. Koyama, H. Tanimoto and S. Mizoguchi in IEEE 1989 Custom Integrated Circuits Conference, pp. 25.2.1-25.2.4, entitled "10.7 MHz Continuous-Time Bandpass filter Bipolar IC".
In FIG. 4, bipolar transistors Q11 and Q12 compose a first differential pair which is driven by a constant current source 71 (current: I.sub.0). Emitters of the transistors Q11 and Q12 are connected in common to the current source 71. Bipolar transistors Q13 and Q14 compose a second differential pair which is driven by a constant current source 72 (current: I.sub.0). Emitters of the transistors Q13 and Q14 are connected in common to the current source 72.
Collectors of the transistors Q11 and Q13 coupled together and collectors of the transistors Q12 and Q14 coupled together form differential output ends of the differential amplifier circuit. Bases of the transistors Q11 and Q12 form differential input ends of the differential amplifier circuit to be applied with an input voltage V.sub.in.
A direct current (DC) voltage source 73 (Voltage: V.sub.k) is provided between the bases of the transistors Q11 and Q13 and a DC voltage source 74 (Voltage: V.sub.k) is provided between the bases of the transistors Q14 and Q12. Thus, bias voltages V.sub.k are respectively applied to the bases of the transistors Q12 and Q13 with their negative ends at the bases of the transistors Q11 and Q14.
An electric current (emitter current) I.sub.E of a p-n junction diode forming a bipolar transistor can be expressed by the following equation (17), where I.sub.g is the saturation current, k.sub.B is Boltzmann's constant, q is the unit electron charge, V.sub.BE is a base-to-emitter voltage of the transistor and T is absolute temperature. EQU I.sub.g =I.sub.S [exp {(qV.sub.BE)/(k.sub.B T)}-1] (17)
Here, if the thermal voltage V.sub.T is defined as V.sub.T =kT/q, as V.sub.BE &gt;&gt;V.sub.T, when exp(V.sub.BE /V.sub.T)&gt;&gt;1 in the equation (17), the emitter current I.sub.E can be approximated as follows; EQU I.sub.E .apprxeq.I.sub.S exp (V.sub.BE /V.sub.T) (18)
As a result, collector currents I.sub.C11 and I.sub.C12 of the transistors Q11 and Q12 can be obtained as follows:
Base-to-emitter voltages of the transistors Q11 and Q12 are expressed as EQU V.sub.BE11 =V.sub.T ln (I.sub.C11 /Is) (19-1)
and EQU V.sub.BE12 =V.sub.T ln (I.sub.C12 /Is) (19-2)
Here, the difference between the voltages V.sub.BE11 and V.sub.BE12 is defined as V.sub.1, or V.sub.BE11 -V.sub.BE12 =V.sub.1. Then, the sum of the collector currents I.sub.C11 and I.sub.C12 is expressed as I.sub.C11 +I.sub.C12 =.alpha..sub.F I.sub.E where .alpha..sub.F is the DC common-base current gain factor. Therefore, the collector currents I.sub.C11 and I.sub.C12 can be given as the following equations (20-1) and (20-2), respectively. EQU I.sub.C11 =(.alpha..sub.F I.sub.0)/{1+exp (-V.sub.1 /V.sub.T)}(20-1) EQU I.sub.C12 =(.alpha..sub.F I.sub.0)/{1+exp (V.sub.1 /V.sub.T)}(20-2)
From the equations (20-1) and (20-2), the difference .increment.I.sub.1 between the collector currents I.sub.C11 and I.sub.C12 is given as EQU .increment.I.sub.1 =I.sub.C11 -i.sub.C12 =.alpha..sub.F I.sub.0 tan h{V.sub.1 /(2V.sub.T)} (21)
The transconductance G.sub.m1 is expressed by differentiating the difference .increment.I.sub.1 by the voltage V.sub.1 as the following equation (22). EQU G.sub.m1 =d(.increment.I.sub.1)/dv.sub.1 ={(.alpha..sub.F I.sub.0)/(2V.sub.T)}[1/}cos h.sup.2 (V.sub.1 /(2V.sub.T))}](22)
In the equation (22), the difference V.sub.1 between the base-to-emitter voltages V.sub.BE11 and V.sub.BE12 is defined as V.sub.1 =V.sub.in -V.sub.k where V.sub.k is the offset bias voltage described above.
With the second differential pair of the transistors Q13 and Q14, similarly, the difference .increment.I.sub.2 between the collector currents I.sub.C13 and I.sub.C14 of the transistors Q13 and Q14 can be expressed as the following equation (23). EQU .increment.I.sub.2 =I.sub.C13 -I.sub.C14 =.alpha..sub.F I.sub.0 tan h{V.sub.2 /(2V.sub.T)} (23)
In the equation (23), the difference V.sub.2 between the base-to-emitter voltages V.sub.BE13 and V.sub.BE14 is defined as V.sub.2 =V.sub.in -V.sub.k, so that the sum .increment.I of the current differences .increment.I.sub.1 and .increment.I.sub.2 can be given by the following equation (24). ##EQU7##
The sum G.sub.m of the transconductances G.sub.m1 and G.sub.m2 of the first and second differential pairs can be given by the following equation (25). ##EQU8##
The transconductance G.sub.m1 in the equation (22) shows the maximally flat characteristic when V.sub.K =1.3137 V.sub.T. FIG. 5 shows the transconductance characteristics of the differential amplifier circuit. It is seen from FIG. 5 that the fluctuation of the transconductance is limited to -1% or less when .vertline.V.sub.in .vertline..ltoreq.V.sub.T.
The conventional differential amplifier circuits described above have the following problems. With the differential amplifier circuit shown in FIG. 1, since the circuit has the transconductance fluctuation about 3%, it cannot be employed to applications requiring the fluctuation less than 3%, which means that application fields of the circuit is narrow. In addition, since the differential output current is expressed as the difference between the drain current difference, the current efficiency with respect to the driving currents is low.
With the conventional differential amplifier circuit shown in FIG. 3, the differential pair composing the squaring circuit is realized by an MOS transistor with the transconductance parameter k.sub.0 and n in number of the MOS transistors with the transconductance parameter k.sub.0 which are connected in parallel. Therefore, the chip occupation area is expanded and the current consumption increases due to a large number of elements.
For example, choosing k'=k.sub.0 /2 in the equation (15), we get n=1+2/3.sup.1/2 .apprxeq.2.155. Therefore, to obtain a very good transconductance linearity, each of the unbalanced differential pairs must be composed of 431 in number of unit transistors and 200 in number of the unit transistors, which requires a very large chip occupation area. Thus, the conventional differential amplifier circuit shown in FIG. 3 is not practical.
With the differential amplifier circuit shown in FIG. 4, the input voltage range is not wide to be satisfied.